| from | 06-10-202113:00 |
| until | 06-10-202114:00 |
| duration | 1 hour |
| place | Fraunhofer IIS/EAS |
| city | Dresden, Deutschland |
| name | Ms. Dr. Katja Lohmann-SchwitaleFraunhofer IIS/EAS |
| phone | +49 351 4640 726 |
| katja.lohmann-schwitale@eas.iis.fraunhofer.de |
Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specs and tapeout schedules that are not easy to meet. Therefore, we continuously identify and work on design concepts and tools that support the designers in both design efficiency and risk management. In this webinar, we will give you an insight into some of these solutions.