| from | 04-05-202216:00 |
| until | 04-05-202217:00 |
| duration | 1 hour |
| place | Fraunhofer IIS/EAS |
| address | Münchner Straße |
| city | 01187 Dresden, Deutschland |
| name | Ms. Dr. Katja Lohmann-SchwitaleFraunhofer IIS/EAS |
| phone | +49 351 45691 154 |
| katja.lohmann-schwitale@eas.iis.fraunhofer.de |
Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specs and tapeout schedules that are not easy to meet. Especially when targeting various applications or multiple PDKs, initial efforts, design time, and risks increase. In this webinar, we will give you an insight into approaches to ease IP reuse across both PDKs and specifications by means of analog automation.